1. Field of the Invention
The present invention relates to an electrophoretic display device, and more particularly, to an electrophoretic display device being capable of preventing a defect, for example, a crack, on an electric signal line or an electrode, and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically included liquid crystal display (LCD) devices, plasma display panels (PDPs) and organic electro-luminescence displays (OLEDs). However, to meet consumer's requirements, various display devices are introduced.
Particularly, properties of a light weight, a thin profile, a high efficiency and a full color moving image displaying are required in the display device. To meet the properties, an electrophoretic display device is suggested. The electrophoretic display device uses a phenomenon that charged particles move to an anode or a cathode. The electrophoretic display device has advantages in a contrast ratio, a response time, a full color display, a cost, mobility and so on. Different from the LCD device, the electrophoretic display device does not require a polarizer, a backlight unit, a liquid crystal layer and so on. Accordingly, the electrophoretic display device has an advantage in production costs.
FIG. 1 is a cross-sectional view illustrating a driving method for the related art electrophoretic display device. In FIG. 1, the related art electrophoretic display device 1 includes a first substrate 11, a second substrate 36 and an ink layer 57 interposed therebetween. The ink layer 57 includes capsules 63, and each capsule 63 has a plurality of white-dyed particles 59 and a plurality of black-dyed particles 61 therein. The white-dyed and black-dyed particles 59 and 61 are negatively and positively charged by a condensation polymerization reaction, respectively.
A plurality of pixel electrodes 28, which are connected to a thin film transistor (not shown), are disposed under the first substrate 11 and in each pixel region (not shown). Each of the pixel electrodes 28 has a positive voltage or a negative voltage. When the capsules having various sizes are formed, a filtering process is performed to obtain capsules having a uniform size.
When a positive or negative voltage is applied to the ink layer 54, the white-dyed particles 59 and the black-dyed particles 61 in the capsules 63 move according to polarities of the applied voltage. When the black-dyed particles 61 move upward, a black color is displayed. When the white-dyed particles 59 move upward, a white color is displayed.
FIG. 2 is a schematic cross-sectional view of the related art electrophoretic display device. In FIG. 2, the related art electrophoretic display device 1 includes a first substrate 11, a second substrate 36 and an electrophoretic film 60 interposed therebetween. The electrophoretic film 60 includes an ink layer 57, first and second adhesive layers 51 and 53, and a common electrode 55. The ink layer 57 is disposed between the first and second adhesive layers 51 and 53. Each of the first and second adhesive layers 51 and 53 is formed of a transparent material. The common electrode 55 is disposed under the second adhesive layers 53 to face the ink layer 57. The ink layer 57 includes capsules 63, and each capsule 63 has a plurality of white-dyed particles 59 and a plurality of black-dyed particles 61 therein. The white-dyed and black-dyed particles 59 and 61 are negatively and positively charged, respectively.
The second substrate 36 may be formed of a transparent plastic or a glass, and the first substrate 11 may be formed of an opaque stainless steel. The first substrate 11 may be also formed of a transparent plastic or a glass. A color filter layer 40 of red (R), green (G) and blue (B) colors sub-color filters is formed under an entire surface of the second substrate 36. On the first substrate 11, a gate line (not shown) and a data line (not shown) are formed. The gate and data lines cross each other to define a pixel region P. A thin film transistor (TFT) Tr is formed at a crossing portion of the gate and data lines. The TFT Tr is disposed in each pixel region P. The TFT Tr includes a gate electrode 14, a gate insulating layer 16, a semiconductor layer 18 including an active layer 18a and an ohmic contact layer 18b, a source electrode 20 and a drain electrode 22. The gate and source electrodes are connected to the gate and data lines, respectively, and the gate insulating layer 16 covers the gate electrodes 14. The semiconductor layer 18 is disposed on the gate insulating layer 16 and overlaps the gate electrode 14. The source and drain electrodes 20 and 22 are disposed on the semiconductor layer 18 and spaced apart from each other.
A passivation layer 26 including a drain contact hole 27 is formed over the TFT Tr. The drain contact hole 27 exposes a portion of the drain electrode 22. A pixel electrode 28 is disposed on the passivation layer 26 and in each pixel region P. The pixel electrode 28 is connected to the drain electrode 22 through the drain contact hole 27. The pixel electrode 28 may be formed of a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
The electrophoretic display device 1 having the above elements uses ambient light, for example, natural light or room electric light, as a light source. The electrophoretic display device 1 can display images by inducing a position change of the white-dyed particles 59 and the black-dyed particles 61 in the capsule 63 depending on a polarity of a voltage applied to the pixel electrode 28.
A fabricating process for the electrophoretic display device may be classified as an array process and a film laminating process. The array substrate 11, where array elements, for example, the TFT Tr, the pixel electrode 28, and so on, are formed, is fabricated in the array process. In the film laminating process, an electrophoretic film is attached onto the array substrate 11 such that the electrophoretic display device 1 is manufactured.
FIG. 3 shows a film laminating process for fabricating the related art electrophoretic display device, and FIG. 4 is a cross-sectional view of the related art electrophoretic display device including a display region and a non-display region.
Referring to FIGS. 3 and 4, after forming the array substrate 11, where array elements, for example, the TFT Tr, the pixel electrode 28, and so on, are formed, an electrophoretic film 60 including an ink layer 57 is attached on a display region DA and a portion of a non-display region NA of the array substrate 11 by the film laminating process. Although not shown, in the non-display region NA, a gate and data pad electrodes for connection to an external driving circuit board (not shown) for driving the TFT Tr and the pixel electrode 28 in the display region DA, a gate link line 24 for connecting the gate pad electrode to the gate line, a data link line for connecting the data pad electrode to the data line, a common connection line 15 for applying a common voltage, a low gate voltage line for applying a gate low voltage, and an electrostatic preventing circuit are formed. Since there is no element for directly participating in an image displaying and the gate and data pad electrodes should be exposed for connection to the external driving circuit board, it is not required to form the electrophoretic film 60 in the non-display region NA. However, considering mis-aligning, the electrophoretic film 60 is formed on a portion of the non-display region NA adjacent to the display region DA.
Unfortunately, there are some problems. Since the gate link line 24 is formed at the starting point of attaching the electrophoretic film 60, there is strong stress on the gate link line 24 because of a roll 90 for attaching the electrophoretic film 60 onto the array substrate 11. Or, when there are particles in an end side of the electrophoretic film 60, there are cracks on the gate link line 24, an electrode of a driving element in the display region DA, or the gate insulating layer 16 under the gate link line 24 because of stress resulted from the particles.
If there is strong stress on the gate link line 24 during the film laminating process, the gate link line 24 may be perfectly cut such that a signal from the external driving circuit board can not be applied to the gate line connected to the gate link line 24. In addition, an insulating property of the gate insulating layer 16 between the gate link line 24, on which the cracks are formed, and another electric line, for example, the common connection line 15, the low gate voltage line (not shown), under the gate insulating layer is destructed such that an electric shortage problem is caused. Namely, the array substrate can not be driven.
Referring back to FIG. 4, a passivation layer 26, which has a relatively high thickness of about 2 to 4 micrometers and is made of an organic insulating material, is formed in the display region DA, while there is no passivation layer in the non-display region NA.
To minimize these problems, it is possible for the elements, for example, the electrostatic preventing circuit, except the link line to be formed in an outer portion of the non-display region NA. Unfortunately, this solution causes an increase of a processing margin and a size of the non-display region NA. It is against the tendency for decreasing a size of the non-displaying region NA. In addition, since the link line should be formed to be extended from the display region DA to the non-display region NA, there is a limitation to preventing these problems.